1. Field of the Invention
The present invention relates to a diagnostic apparatus for a data processing system and, more particularly, to a chip level diagnostic apparatus incorporating a scan design into a latch-based system.
2. Description of the Relevant Art
In the past, digital circuits contained within an IC chip were tested manually because access to individual components was possible. As time progressed, the number of devices per chip increased, causing a corresponding decrease in the ratio of the number of IC pins to the number of components on the chip. As a result, access to individual devices became more difficult, if not impossible.
As testing and maintenance costs increased beyond acceptable limits, designers attempted to enhance the observability and controllability of each chip to facilitate testing. Observability refers to the ease with which the state of internal signals can be determined. Controllability refers to the ease of producing a specific internal signal value. The most direct way to increase the observability or controllability of a circuit design is to introduce test points, or additional circuit inputs and outputs, into the chip for use during testing. For circuit boards, the cost of test points is often well justified. On the other hand, the cost of test points for ICs can be prohibitive because of IC pin limitations. Consequently, techniques have evolved which use scan paths to permit access to the internal nodes of a circuit without requiring a separate external connection for each node accessed.
In the scan path technique, a circuit is designed so that it has two modes of operation: one that is the normal functional mode, and the other that is a test mode in which circuit memory (storage) elements, typically combinational circuitry input and output storage elements, are interconnected into a shift register chain for forming scan units associated with each set of combinational logic. With the circuit in a test mode, it is possible to shift an arbitrary test pattern into the input elements. By returning the circuit to a normal mode for one clock period, the combinational circuitry can act upon the shift register contents and then store the results in the output elements. If the circuit is then placed into a test mode, it is possible to shift out the contents of the shift register and compare the contents with the correct response.
One way of implementing a scan path is to interconnect the circuit flip-flops to form a shift register. An important characteristic of flip-flops is that a shift register can be constructed by connecting the output of one flip-flop directly to the data input of the next flip-flop. Unfortunately, flip-flop based scan paths are not efficient or not easy to implement in some technologies, e.g., MOS technology, and there are circumstances when the system must be run using multiple non-overlapping pulse trains. Furthermore, scan paths utilizing flip-flops are sensitive to variations in the clocking signal and hence require careful consideration of clock skew, signal propagation time, and other hardware factors which may be extremely difficult to control.
Another scan path technique uses level sensitive elements, e.g., latches, rather than flip-flops, as the shift register elements. An example of the technique is "level sensitive scan design" (LSSD), used by IBM. Unfortunately, it is not possible to reconfigure system latches directly into a shift register for test purposes. Instead, the conversion of a latch register into a shift register requires converting each latch into a specialized dual input latch and placing an extra latch between each register stage. The resulting structure requires three clocks to operate, and each clock must be carefully controlled and operated at different times, depending on whether the system is in normal or test mode. The controlling logic adds to clock skew.
The following publications discuss techniques of Level Sensitive Scan Design and are considered relevant to the present invention. They are incorporated herein by reference. Donald Komonytsky, "LSI Self Test Using Level Sensitive Scan Design and Signature Analysis," 1982 IEEE Test Conference, Paper 14.3; E.B. Eichelberger, T.W. Williams, "A Logic Design Structure For LSI Testability," #14 Design Automation Conference, 1977; T.W. Williams, "Design for Testability --A Survey," IEEE Transactions on Computers, Vol. C-31, No. 1, January 1982; Konemann, Mucha & Zwiehoff, "Built-In Test for Complex Digital Integrated Circuits," IEEE Journal of Solid State Circuits, Vol. SC-15, No. 3, June 1980; E. J. McCluskey, "A Survey of Design for Testability Scan Techniques," VLSI System Design Magazine, Semicustom Design Guide, Summer 1986.